Multiple verification suites and work arounds (VHDL)

Recently, I was evaluating a verification suite, Riviera-PRO by Aldec. The problem I ran into was that our current environment is ModelSim's signal_spy was being used all over the place to spy and force signals. The problem resides in that I have found no apparent way to "pre-process" VHDL files in modelsim. Riviera allows you to do so with --vhdl_compile_off and --vhdl_compile_on pragma
To remedy this, I took Riviera's near equivalent signal_agent and signal_spy and combined them into my own proprietary package for lack of a better name sim_utils. This is then implemented as follows:
1) Both Aldec and Riviera procedures are defined in the file allowing use of either format.
2) There are two separate sim_utils libraries. One of which will be called at compile time depending whether the compiler is through Aldec or Modelsim.

Implementation:

First, the existing procedures must be mapped so that they can still be accessed. i.e. we want to just call the modelsim procedures within a modelsim environment.
Here is an example of an alias.

ALIAS init_signal_spy IS modelsim_lib.util.init_signal_spy [STRING, STRING, INTEGER, INTEGER];

What this does is allows the calling of init_singal_spy as is, under modelsim.

Next, init_signal_spy is implemented under Aldec. Create a procedure init_signal_spy with the same parameters as Modelsim's version, this will make it so that the only lines that will need to change are the library lines.

PROCEDURE init_signal_spy(
   scr_object    : IN STRING;
   dest_object   : IN STRING;
   verbose       : IN INTEGER := 0;
   control_state : IN INTEGER := -1) IS
BEGIN
   ASSERT (control_state = -1)
      REPORT "Control State is unsupported under Aldec tools."
      SEVERITY WARNING;
   signal_agent(src_object,dest_object,verbose);
END PROCEDURE init_signal_spy;